I. Field of the Disclosure
The technology of the disclosure relates generally to operational amplifiers, and particularly to slew rate variation in an operational amplifier output caused by frequency compensation.
II. Background
An operational amplifier (also referred to as an “op-amp”) is a device that receives differential input signals and generates an output voltage based on a gain of the op-amp. A wide variety of circuit functions may be accomplished using op-amps. Thus, a vast array of electronic devices employ op-amps in their circuits. However, manufacturing process variations in an op-amp's internal components may generate an unintended internal offset voltage that affects the output voltage in an undesirable manner. The output voltage of an op-amp is calculated by multiplying an op-amp's gain by a sum of the voltage difference of the differential input signals and any such offset voltage present. For example, an op-amp receiving a first differential input V1 and a second differential input V2, and having an offset voltage VOFFSET, generates an output voltage VOUT equal to A (V1−V2+VOFFSET), where ‘A’ represents the op-amp's gain. One way to reduce the effects of an op-amp's offset voltage is to use an auto-zeroing operational amplifier (also referred to as an “auto-zeroing op-amp”). An auto-zeroing op-amp includes circuitry that attenuates the effects that any offset voltage of the op-amp has on the output voltage VOUT.
In this regard, FIG. 1 illustrates an exemplary auto-zeroing op-amp 10. In this example, the auto-zeroing op-amp 10 includes a first differential input 12, a second differential input 14, a main op-amp 16, and a nulling op-amp 18. The main op-amp 16 provides the primary signal amplification for the auto-zeroing op-amp 10, while the nulling op-amp 18 reduces the effects of the main op-amp's 16 offset voltages. The main op-amp 16 generates an output voltage VOUT on a main voltage output node 20 based on an amplified sum of a differential of first main differential inputs 22(1), 22(2) and an associated offset voltage. To reduce the effects of the offset voltage of the main op-amp 16 being applied to the output voltage VOUT, the main op-amp 16 includes second main differential inputs 24(1), 24(2). A clock signal CLK activates and deactivates switches 26(1)-26(4) that control input voltages received by the nulling op-amp 18, as well as a correction voltage received on the second main differential input 24(1) of the main op-amp 16. In this regard, the switches 26(1)-26(4) are employed to change the input voltages to the nulling op-amp 18 and the main op-amp 16 in a way that causes the output voltage of the nulling op-amp 18 to attenuate the offset voltages of the main op-amp 16.
More specifically, during a first phase of the clock signal CLK, switches 26(1), 26(2) are closed and switches 26(3), 26(4) are opened. Closing switch 26(1) causes both first nulling differential inputs 28(1), 28(2) of the nulling op-amp 18 to each receive the same input voltage. Closing switch 26(2) causes an output voltage known as VOUT-NULL-P1 to be generated on a nulling voltage output node 30 of the nulling op-amp 18, which is provided to a second nulling differential input 32(2). A reference voltage VAZREF is provided to a second nulling differential input 32(1). Providing voltage YOUT-NULL-P1 to the second nulling differential input 32(2) of the nulling op-amp 18 attenuates the effects of the nulling op-amp's 18 offset voltage during the first phase of the clock signal CLK. Voltage VOUT-NULL-P1 is also provided to a capacitor 34(1), which stores VOUT-NULL-P1 as a nulling correction voltage. In this manner, the capacitor 34(1) will provide voltage VOUT-NULL-P1 to the second nulling differential input 32(2) to attenuate the effects of the nulling op-amp 18 during the second phase of the clock signal CLK.
During a second phase of the clock signal CLK, switches 26(3), 26(4) are closed, and switches 26(1), 26(2) are opened. Closing switch 26(3) causes the nulling op-amp 18 to receive input voltages from the first differential input 12 and the second differential input 14. Closing switch 26(4) results in a voltage VOUT-NULL-P2 being generated on the nulling voltage output node 30, thereby causing the nulling op-amp's 18 output voltage to change from VOUT-NULL-P1 to VOUT-NULL-P2. Voltage VOUT-NULL-P2 is provided to the second main differential input 24(1) of the main op-amp 16, which attenuates the effects of the main op-amp's 16 offset voltage during the second phase of the clock signal CLK. Voltage VOUT-NULL-P2 is also provided to a capacitor 34(2), which stores VOUT-NULL-P2 as a main correction voltage. The reference voltage VAZREF is provided to a second main differential input 24(1). In this manner, the capacitor 34(2) provides voltage VOUT-NULL-P2 to the second main differential input 24(1) to attenuate the effects of the offset voltage of the main op-amp 16 during the first phase of the clock signal CLK.
While the auto-zeroing op-amp 10 in FIG. 1 may reduce the effects of the main op-amp's 16 offset voltages on the output voltage VOUT, this design can lead to other issues. In particular, the nulling op-amp 18 in FIG. 1 employs an internal frequency compensation circuit to achieve loop stability with respect to its output voltage. To stabilize the output voltage VOUT, the frequency compensation circuit is coupled to the nulling voltage output node 30. The frequency compensation circuit stores a voltage associated with the output voltage of the nulling op-amp 18 to compensate for stability issues of the nulling op-amp 18. However, as previously described, when the input voltages to the nulling op-amp 18 change between the first and second phases of the clock signal CLK, the nulling op-amp 18's output voltage changes (i.e., slews) from VOUT-NULL-P1 to VOUT-NULL-P2 over a period of time. The change in the nulling op-amp's 18 output voltage from VOUT-NULL-P1 to VOUT-NULL-P2 causes the voltage stored in the frequency compensation circuit to change from a voltage associated with the first phase of the clock signal CLK to a voltage associated with the second phase of the clock signal CLK. Because the frequency compensation circuit is coupled to the nulling voltage output node 30, the output voltage generated by the nulling op-amp 18 is used to slew the nulling op-amp's 18 output voltage from VOUT-NULL-P1 to VOUT-NULL-P2. Large slew times of the nulling op-amp 18's output voltage causes erroneous voltage levels to appear in the output voltage of the main op-amp 16 when the clock signal CLK transitions phases. Therefore, it would be advantageous to provide op-amps that include frequency compensation, whether for auto-zeroing op-amps or other applications, without incurring a relatively large slew time of an op-amp's output voltage.